A Pipelined Karatsuba-Ofman Multiplier over GF(397) Amenable for Pairing Computation

We present a subquadratic ternary field multiplier based on the combination of several variants of the Karatsuba-Ofman scheme recently published. Since one of the most relevant applications for this kind of multipliers is pairing computation, where several field multiplications need to be computed at once, we decided to design a k-stage pipeline structure for k = 1, . . . , 4, where each stage is composed of a 49-trit polynomial multiplier unit. That architecture can compute an average of k field multiplications every three clock cycles, which implies that our four-stage pipeline design can perform more than one field multiplication per clock cycle. When implemented in a Xilinx Virtex V XC5VLX330 FPGA device, this multiplier can compute one field multiplication over GF(3) in just 11.47ns. keyword: Finite field arithmetic; Field Multiplier; cryptography